BOOLEY

Open-source agentic RTL IDE for FPGA and ASIC work

Package booley-rtl on PyPI. Works with Claude Code or Codex.

1Description

Booley turns Claude Code or Codex into a capable RTL assistant. It runs the Developer Agent in a sandbox, hands it real EDA tools, and checks its work against your acceptance criteria: passing tests, area and timing budgets, cycle counts, coverage, and more.

Quick start
$ pipx install booley-rtl
$ booley bootstrap
Requirements, upgrades, and troubleshooting: installation guide.
1 Plain-language request
Plain-language request
Describe the problem in your own words. No commands, no scripts.
2 Answered from the trace
Answered from the trace
bwave queries the recorded waveform instead of guessing from RTL.
3 Typed results, not raw logs
Typed results, not raw logs
Each Flow returns PASS or FAIL plus metrics, so the fix is checked, not claimed.
4 Parallel Goal Mode session
Parallel Goal Mode session
Codex works on a separate task toward Goals that Booley checks itself.
5 Booley Dashboard
Booley Dashboard
Every session’s activity, Goal progress, running Jobs, and Sandbox health.
6 Waveform viewer
Waveform viewer
The sim Flow’s trace, cursor on the dropped beat at cycle 214.
7 Sandbox
Sandbox
Status bar: the window runs in the Booley Dev Container.
Figure 1. Booley in VS Code (illustration).

2Features

Typed EDA Flows

sim, lint, synth, and fpga replace per-repo glue Tcl scripts. Each Flow runs an EDA job end to end and returns a structured result: pass/fail plus metrics such as area, timing, or cycle counts, not just raw logs. Flows are built on FuseSoC, and the interface stays the same across tools and projects: sim stays sim whether it runs Verilator today or Xcelium tomorrow.

Reproducible team environment

Configure the project once, and its Docker environment supplies the same pinned EDA stack, agent tooling, and system dependencies to everyone on the project (why Docker).

One VS Code window

RTL work is usually scattered across editors, tool-specific commands, build environments, logs, and waveform viewers. Booley puts RTL, agent sessions, terminals, EDA runs, waveforms, and the Booley Dashboard side by side in one VS Code window.

Sandboxed Developer Agent

Booley treats the agent like a talented junior engineer. It can write RTL and testbenches, but it is inexperienced with EDA tools, prone to questionable design decisions, and too risky to give unrestricted host access. So the agent and every command it runs stay inside a Docker container with restricted mounts and network access, and its work goes through explicit specifications, automated checks, and human review. That lets it work unattended.

Goal Mode

You set mandatory Goals up front, such as SYNTH:synth_fifo (area increase ≤ 10%) or COVERAGE:sim_fifo (line ≥ 90%, tests all). Goals cover passing tests, lint, area, timing, cycle counts, coverage, mutation testing, and code review. Booley checks each one in deterministic code against fresh recorded Flow results, not against the agent’s claim of success (details).

Waveform queries

bwave lets the agent find, sample, snapshot, and measure real simulation traces. Ask “When did data_o equal 0xDEADBEEF?” and it answers from simulation data instead of guessing from RTL.

Booley architecture VS Code opens an agent session (Claude Code or Codex, in Interactive or Goal Mode) inside the Booley devcontainer Sandbox. Example requests: debug the backpressure test failure on the heavy target; compare synth area between commits; run a security review on the control unit module. The agent enters and finishes Goals, such as LINT:lint_fifo with no unwaived findings, SIM:sim_fifo with all selected tests passing, REVIEW:rtl_bugs clean on Target sim_fifo, SYNTH:synth_fifo with area increase at most 10 percent, and FPGA:fpga_fifo with Fmax at least 100 MHz. The agent edits the Project Git worktree (RTL and testbenches) and calls the MCP Server, Booley Flows, which drives EDA tools through the Edalize API: a linter (Verilator), a simulator (Verilator or Icarus Verilog), and a synthesis tool (Yosys). The MCP Server sends evidence to the Goals and calls Specialist Agents: reviewer for single-focus code review, mutation_tester for mutation testing, and coverage_analyst to explain coverage and suggest next steps. Outside the Sandbox, an Egress Proxy Container lets the agent reach the internet for the LLM provider only, and a heavy tool installed on the host (Vivado) is mounted read-only. The Internet LLM provider only Egress Proxy Container VS Code Booley devcontainer Sandbox Agent session (Claude Code or Codex) Interactive or Goal Mode Examples: “Debug the backpressure test failure on heavy target” “Compare synth area between the following commits: ...” “Run security review on the control unit module” Goals LINT:lint_fifo(no unwaived findings) SIM:sim_fifo(all selected tests pass) REVIEW:rtl_bugs(clean, Target sim_fifo) SYNTH:synth_fifo(area increase ≤ 10%) FPGA:fpga_fifo(Fmax ≥ 100 MHz) enter / finish edits Project Git worktree (RTL, TB) MCP MCP Server: Booley Flows (calls EDA tools using Edalize API) evidence Specialist Agents • reviewer: single-focus code review (bugs, spec, protocol, security, ...) • mutation_tester: mutation testing • coverage_analyst: explains coverage, suggests next steps EDA tools Linter (Verilator) Simulator (Verilator / iverilog) Synthesis Tool (Yosys) Heavy tool installed on Host (Vivado) Read-only Mount Booley architecture The Internet LLM provider only Egress Proxy Container VS Code Booley devcontainer Sandbox Agent session (Claude Code or Codex) Interactive or Goal Mode Examples: “Debug the backpressure test failure on heavy target” “Compare synth area between the following commits: ...” “Run security review on the control unit module” edits enter / finish MCP Goals LINT:lint_fifo(no unwaived findings) SIM:sim_fifo(all selected tests pass) REVIEW:rtl_bugs(clean, Target sim_fifo) SYNTH:synth_fifo(area increase ≤ 10%) FPGA:fpga_fifo(Fmax ≥ 100 MHz) Project Git worktree (RTL, TB) MCP Server: Booley Flows (calls EDA tools using Edalize API) evidence Specialist Agents • reviewer: single-focus code review (bugs, spec, protocol, security, ...) • mutation_tester: mutation testing • coverage_analyst: explains coverage, suggests next steps EDA tools Linter (Verilator) Simulator (Verilator / iverilog) Synthesis Tool (Yosys) Heavy tool installed on Host (Vivado) Read-only Mount
Figure 2. Booley architecture.

3Flow characteristics

Table 1. Booley Flows (see supported EDA tools for versions)

FlowToolsConditions and notesStatus
simVerilator, Icarus Verilogcocotb testbenches work as they areSupported
lintVerilator, VeribleSupported
synthYosys, OpenROADPhysical timing on Nangate45. A PPA estimate, not tape-outSupported
fpgaAMD Vivado 2025.2From your own licensed install, not included in the containerSupported
bwaveBooley B-WaveWaveform queries for the agent: find, sample, snapshot, measureSupported
simSynopsys VCS, Cadence XceliumIn progress

4Absolute maximum ratings

Table 2. Limits of use

ParameterRatingNotes
Architecture and design decisionsMade by youBooley will not design hardware for you. You write the architecture and specs; it handles the grunt work.
Operator experienceDigital design requiredBooley assumes you can read RTL, judge a waveform, and know what a sane result looks like.
HDL inputSystemVerilog, VerilogVHDL and UVM are not supported.
IDE shellStock VS CodeNo custom editor chrome yet. Native UI is on the roadmap.
Setup effortOnce per projectComplex flows or heavy licensed tools may need project-specific work. Every later session builds on it.
MaturityWork in progressExpect occasional bugs and rough edges in the UI.

Operating beyond these ratings will not damage your silicon, but it will waste your afternoon.

5Application notes

AN-001

Why AI agents struggle with RTL debugging, and what helps

In CaliptraA large open-source system on chip from CHIPS Alliance. It is a hardware root of trust: a security block with its own RISC-V processor and firmware., an agent found a RISC-V processor bug within minutes, then spent most of an hour reproducing it. Invisible internal signals and long-running simulations explain much of that time; tools aimed at them, plus a repeatable build, cut it from 56 minutes to 21.

boldaxolotl, 16 October 2026. Read the application note

With Booley
21.3 min
Claude Code alone
55.8 min

Mean completion time, ten trials per setup.

6How it is built

Booley was designed and is maintained by a hardware engineer, not a career software engineer. Its first-party code was written by Claude and Codex, but this is not vibe-coding: I define the architecture and specifications, weigh tradeoffs, review plans and code, and make the final engineering decisions.

Every change goes through separate agent and human reviews, with isolated branches, type checking, linting, automated tests, coverage requirements, and CI (coding principles). Reviews from experienced software engineers are especially welcome.